CPRE=MCK, UPDS=UPDATE_AT_PERIOD, CES=SINGLE_EVENT, CPOL=LOW_POLARITY, CALG=LEFT_ALIGNED
PWM Channel Mode Register
| CPRE | Channel Pre-scaler 0 (MCK): Peripheral clock 1 (MCK_DIV_2): Peripheral clock/2 2 (MCK_DIV_4): Peripheral clock/4 3 (MCK_DIV_8): Peripheral clock/8 4 (MCK_DIV_16): Peripheral clock/16 5 (MCK_DIV_32): Peripheral clock/32 6 (MCK_DIV_64): Peripheral clock/64 7 (MCK_DIV_128): Peripheral clock/128 8 (MCK_DIV_256): Peripheral clock/256 9 (MCK_DIV_512): Peripheral clock/512 10 (MCK_DIV_1024): Peripheral clock/1024 11 (CLKA): Clock A 12 (CLKB): Clock B |
| CALG | Channel Alignment 0 (LEFT_ALIGNED): Left aligned 1 (CENTER_ALIGNED): Center aligned |
| CPOL | Channel Polarity 0 (LOW_POLARITY): Waveform starts at low level 1 (HIGH_POLARITY): Waveform starts at high level |
| CES | Counter Event Selection 0 (SINGLE_EVENT): At the end of PWM period 1 (DOUBLE_EVENT): At half of PWM period AND at the end of PWM period |
| UPDS | Update Selection 0 (UPDATE_AT_PERIOD): At the next end of PWM period 1 (UPDATE_AT_HALF_PERIOD): At the next end of Half PWM period |
| DPOLI | Disabled Polarity Inverted |
| TCTS | Timer Counter Trigger Selection |
| DTE | Dead-Time Generator Enable |
| DTHI | Dead-Time PWMHx Output Inverted |
| DTLI | Dead-Time PWMLx Output Inverted |
| PPM | Push-Pull Mode |